1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming copper-based conductive structures using a chemical mechanical planarization (CMP) integration scheme that eliminates exposure of copper to interlayer dielectric (ILD).
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that, to a great extent, substantially determines the performance capability of integrated circuit devices employing such transistors. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreased in size to enhance the performance of the semiconductor device and the overall functionality of the circuit.
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features. Generally, decreasing the size of, for instance, the channel length of a transistor typically results in higher drive current capabilities and enhanced switching speeds. Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate between adjacent transistors. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is correspondingly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” or ultra-low-k (ULK) dielectric materials (for example, materials having a dielectric constant less than 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using aluminum for the conductive lines and vias. The use of low-k dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk, as compared to other dielectric materials with higher dielectric constants.
However, the use of copper metallization systems with such low-k dielectric materials can be problematic. For example, after Back End of Line (BEOL) copper CMP, there is usually some amount of residual copper atoms/ions left on the surface (over exposed ILD). This residual copper can result in formation of dendrites due to copper oxidation. The presence of water will accelerate the dendrite growth which becomes a bigger problem for low-k ILD because it is porous and holds moisture. The dendrite can result in connecting copper lines resulting in shorting, capacitance and Time Dependent Dielectric Breakdown (TDDB) issues.
An existing approach to this problem is to deposit an Nblok cap layer after BEOL CMP. However, the queue time needs to be short, for example less than 6 hours. With this approach, the surface is capped before significant dendrite growth occurs. However, the short queue time needed is not ideal or practical for high volume manufacturing.
Another approach requires the use of commercially available chemicals for wafer cleaning, which can slow down the growth of dendrites post copper CMP. However, the use of such chemicals adds steps, complexity and cost to the manufacturing process.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.